This invention relates generally to phase shift masks and more particularly to alignment detection indicia formed on such masks.
As is known in the art, phase shift masks are used to pattern semiconductors with submicron delineations. With phase shift masks, interference of light rays is used to provide a proper mask effect. The phase of the exposed light at the target is controlled such that bright areas are preferably formed 180 degrees out of phase with each other. Dark areas are thus produced between the bright areas by destructive interference.
In general, a phase shift mask is constructed with a repetitive pattern formed on three different distinct layers of material. An opaque layer, such as chrome, provides areas that allow no light transmission (i.e., a highly light reflective layer, or surface). A first transparent layer, such as quartz, provides areas which allow close to 100% of the light to pass through. A transparent phase shifting layer, such as areas etched a predetermined distance into the quartz, provides areas which allow close to 100% of the light to pass through but phase shifted 180 degrees from the light passing through the first transparent layer. The first transparent layer and the transparent phase shifting layer are positioned such that light rays diffracted through each area are canceled out in a darkened area between them. This creates a pattern of dark and bright areas which can be used to clearly delineate desired features on the semiconductor wafer.
One type of such phase shifting mask is formed by providing a quartz substrate 10 (FIGS. 1, 1A and 1B) having a chrome layer 12 formed on an upper surface thereof. A pattern of the described first transparent regions 16 and a first step in forming the transparent phase shifting regions 18 is etched (i.e., "written") into the chrome 12 to expose underlying top surface regions 14 of the quartz 10, as shown in FIGS. 1, 1A and 1B. It is noted that also written into the chrome 12 with the pattern is a first portion of an alignment detection region 20. The first portion of the alignment detection region 20 has a square chrome-quartz interface 24 with four, centrally disposed, square chrome patches 12.sub.1 -12.sub.4 arranged to form a cross-shaped region (i.e., a pair of intersection lines 17a, 17b) between the four square patches 12.sub.1 -12.sub.4.
Next, the pattern of transparent phase shifting regions 18 is completed by etching the pattern of transparent phase shifting regions 18 formed in the first writing step (FIGS. 1. 1A, and 1B) into the underlying, upper surface regions, of the quartz 10 to form recesses 25 into the quartz 10, as shown in FIGS. 2, 2A and 2B. It is also noted that during this second writing step, a cross formed by lines 17'a, 17'b is etched into the upper surface portion of the quartz 10 of region 20, as shown in FIGS. 2A, 2B and 2. It is noted that if the two writing steps produce the transparent phase shifting regions 18 in proper alignment with the first transparent regions 16 the two crosses (i.e., the cross formed by lines 17a, 17b in the first write step, FIG. 1 and the cross formed by lines 17'a, 17'b in the second write step, FIG. 2) will be in alignment (i.e., registration) with each other. The amount of misalignment is determined by passing a light, not shown, through a slit 21 and moving the slit 21 across the surface of the alignment detection region 20 in two steps for each of two orthogonal directions, i.e., the X direction and the Y direction indicated in FIG. 2A.
During the first scanning step, the slit 21 is passed over the surface of the alignment detection region 20 along a first region (i.e., SCAN REGION 1) which passes over the central portion of the alignment detection region 20, i.e., over the four chrome patches 12.sub.1 -12.sub.4. The amount of light reflected by the surface of the alignment detection region 20 is detected and a voltage representative of the amount of such reflected light is produced as a function of time or distance along the alignment detection region 20, as shown in FIG. 2C. It is noted that the light is first reflected by the chrome surface bordering the alignment detection region 20, then by etched and un-etched surface portions of the quartz 10, then by the surfaces of the chrome patches 12.sub.1 -12.sub.4, then by the un-etched surface of the quartz 10 providing line 17a and then the reflections from the surfaces repeat in a symmetrical manner.
The voltage produced by such reflections in scanning SCAN REGION 1 is shown in FIG. 2C. It is noted that the level of the voltage has a first transition A at interface 24, a second transition B at the interface 36 between the leading edges of two patches 12.sub.2 and 12.sub.3 and etched quartz, a third transition C at the interface 40 between the trailing edges of the two patches 12.sub.2 and 12.sub.3 and the un-etched surface of the quartz 10 forming line 17a of the cross, a fourth transition D at the interface 40' between the leading edges of the two patches 12.sub.1 and 12.sub.4 and the un-etched surface of the quartz 10 forming the line 17a of the cross, a fifth transition f at the interface 36' between the trailing edges of patches 12.sub.1, 12.sub.4 and the un-etched quartz, and a sixth transition G at the interface 24.
During the second scanning step, the slit 21, or here pair of slits 21, is passed over the surface of the alignment detection region 20 along a pair of second regions (i.e, SCAN REGION 2) each of which pass over the outer peripheral portion of the alignment detection region 20, i.e., over the surface of the un-etched quartz from line 17'a, then over the surface of the etched quartz and then over the surface of the un-etched quartz. The amount of light reflected by the surface of the alignment detection region 20 is detected and a voltage representative of the amount of such reflected light is produced, as shown in FIG. 2D as a function of time or distance along the alignment detection region 20.
It is noted that the voltage has a first transition H at the interface 24, a second transition I at the interface 42 between the un-etched and etched quartz 10 forming the leading edge of line 17'a, a third transition J at the interface 42' between the un-etched and etched quartz 10 forming the trailing edge of line 17'a, and a fourth transition K at the interface 24.
It is noted that a first notch 50 in the voltage level produced during scanning the SCAN REGION 1 (FIG. 2C) is produced between transitions C and D when from scanning the line 17a of the cross formed during the first write the scan and second notch 52 in the voltage level produced during scanning the SCAN REGION 2 (FIG. 2D) is produced between transitions I and J when from scanning the line 17'a of the cross formed during the second write. Because the line 17a was produced during the same write step as the first transparent regions 16 and line 17'a was produced during the same write as the transparent phase shifting regions 18, if the first transparent portions 16 formed during the first write are properly aligned with the transparent phase shifting portions 18 completed in the second write, the notches 50, 52 will be aligned (i.e, centered) with respect to each other. The amount of deviation between the centers of the voltages notches 50, 52 provides an indication of the misalignment in the X direction. The two scanning steps are also provided along the Y direction to thereby provide a Y misalignment measurement.
In order to obtain sufficient contrast between reflections from the surface of the un-etched quartz and the etched quartz, (i.e., the transitions I and J in FIG. 2D) the scan in SCAN REGION 2 over the un-etched portion of the quartz surface must be sufficiently long to provide a relatively constant signal level against which reflections from the etched portion of the surface can be readily detected. Thus, a relatively large area of the underlying silicon semiconductor material will be exposed by light passing through the quartz. During subsequent photolithography, these large exposed areas result in relatively large trenches being formed in the silicon. These trenches must be at least partially filled and contaminants may become somewhat captured in the trench during a trench filling process. However, the contaminants may become loose and release thereof may adversely effect the devices being fabricated.